/*
 * Copyright (c) 2006-2019, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2021-05-24                  the first version
 */

#include <rthw.h>
#include <rtthread.h>

#include "cw32l010_sysctrl.h"
#include "cw32l010_systick.h"

/*-------------------------- ROM/RAM CONFIG BEGIN --------------------------*/
 
#define ROM_START              ((uint32_t)0x08000000)
#define ROM_SIZE               (64 * 1024)
#define ROM_END                ((uint32_t)(ROM_START + ROM_SIZE))
 
#define RAM_START              (0x20000000)
#define RAM_SIZE               (4 * 1024)
#define RAM_END                (RAM_START + RAM_SIZE)	
	
#define STM32_SRAM1_END         RAM_END	
	
/*--------------------------     GET HEAP SIZE    --------------------------*/
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN      (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN      ((void *)&__bss_end)
#endif
 
#define HEAP_END          STM32_SRAM1_END


#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
/*
 * Please modify RT_HEAP_SIZE if you enable RT_USING_HEAP
 * the RT_HEAP_SIZE max value = (sram size - ZI size), 1024 means 1024 bytes
 */
#define RT_HEAP_SIZE (2048)

//static rt_uint8_t rt_heap[RT_HEAP_SIZE];

//RT_WEAK void *rt_heap_begin_get(void)
//{
//    return rt_heap;
//}

//RT_WEAK void *rt_heap_end_get(void)
//{
//    return rt_heap + RT_HEAP_SIZE;
//}

#endif

void rt_os_tick_callback(void)
{
    rt_interrupt_enter();
    
    rt_tick_increase();

    rt_interrupt_leave();
}



void RCC_Configuration(void)
{
    //SYSCLK = HSI = 48MHz = HCLK = PCLK
    SYSCTRL_HSI_Enable(SYSCTRL_HSIOSC_DIV1);
    SYSCTRL_AHBPeriphClk_Enable(SYSCTRL_AHB_PERIPH_FLASH, ENABLE); 

    SYSCTRL_AHBPeriphClk_Enable(SYSCTRL_AHB_PERIPH_GPIOA, ENABLE);
	SYSCTRL_AHBPeriphClk_Enable(SYSCTRL_AHB_PERIPH_GPIOB, ENABLE);
    SYSCTRL_APBPeriphClk_Enable1(SYSCTRL_APB1_PERIPH_UART2, ENABLE);
}                            


/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
    /* USER CODE BEGIN SysTick_IRQn */
    rt_os_tick_callback();
    /* USER CODE END SysTick_IRQn */
}




/**
 * This function will initial your board.
 */
void rt_hw_board_init(void)
{
// #error "TODO 1: OS Tick Configuration."
    /* 
     * TODO 1: OS Tick Configuration
     * Enable the hardware timer and call the rt_os_tick_callback function
     * periodically with the frequency RT_TICK_PER_SECOND. 
     */
    RCC_Configuration();
	InitTick(USER_KERNAL_FREQUENCY);
	
    /* Call components board initial (use INIT_BOARD_EXPORT()) */
#ifdef RT_USING_COMPONENTS_INIT
    rt_components_board_init();
#endif

#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
    //rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
	rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif
}

#ifdef RT_USING_CONSOLE

static int uart_init(void)
{
#error "TODO 2: Enable the hardware uart and config baudrate."
    return 0;
}
INIT_BOARD_EXPORT(uart_init);

void rt_hw_console_output(const char *str)
{
#error "TODO 3: Output the string 'str' through the uart."
}

#endif

